Beschreibung

Experienced IP/SoC engineer with 10+ years in microelectronics.

I help companies improve the reliability, optimization, and validation of complex systems, from RTL to EDA tools.

✅ Arteris IP: deployment of a performance analysis platform on Magillem, identifying bottlenecks on deep-hierarchy SoCs

✅ Airbus D&S: space design porting (ASIC→FPGA Virtex7), complete development of a customer-validated RF calibration bench

✅ Nokia: IPXACT packaging with Magillem, UVM verification (Questa/VCS), quality improvement (Spyglass, OneSpin), independently on release cycles

I am looking for a cross-functional technical role with an overview of design and integration—FAE, Technical Lead, or Sales.

I am always open to discussions and new connections. Feel free to contact me on LinkedIn or by email:

Sprachen

Französisch
Muttersprachlich oder zweisprachig
Englisch
Muttersprachlich oder zweisprachig

Arbeitsortpräferenzen

Vor Ort möglich

Paris (bis zu 50 km)

Fit Factory Mennecy:
Co-founder & Head of Development
GESUNDHEIT & WELLNESS
Dezember 2024 - Heute (1 Jahr und 6 Monate)
Mennecy, Frankreich
💡 Entrepreneurial project launched in my spare time to explore human health and performance
• Creation of a local wellness club: nutrition, sports, and coaching
• Actions taken: workshops, content creation, prospecting, team management
• Objective: to sustainably improve the energy, confidence, and discipline of my members
• Alongside my job as an engineer, this project challenged me in terms of business and people skills
Gestion de projet Management d'équipe Réseaux sociaux Communication Marketing
Arteris IPD
Senior Validation Engineer
HIGHTECH
Januar 2021 - Januar 2024 (3 Jahre)
Paris, France
🧪 Functional validation of soft IPs integrated into the Magillem tool (IP-XACT), with implementation of automated tests in the CI chain (🧰 Jira, 🐍 Python).
📊 Development of a tool performance analysis platform to detect breakpoints on deep hierarchy SoCs and multiple IPs.
🚀 Contribution to improving the reliability of software deliveries and scalability in complex use cases.
Atlassian JIRA Python Validation Gitlab CI/CD Git
NanoXplore
IP/SoC Engineer
LUFT- & RAUMFAHRT
Januar 2020 - Januar 2021 (1 Jahr)
Sèvres, Frankreich
🧠 Développement d’un générateur de trafic AXI4-Lite programmable en SystemVerilog, intégré à la bibliothèque NanoXplore.
🔁 Synthétisé sur FPGA et utilisé comme outil standard pour la validation interne des IP, ainsi que comme livrable configurable pour les clients.
💡 Participation au design RTL et à la vérification fonctionnelle, avec intégration dans le flow de conception du produit final.
SystemVerilog FPGA ASIC VHDL Spécifications fonctionnelles